Spin-on-glass (SOG) is frequently used for gap fill and planarization of inter-level dielectrics (ILD) in multi-level metalization structures. It is a desirable material for use in low-cost fabrication of IC circuits. Most commonly used SOG materials are of two basic types; an inorganic type of silicate based SOG and an organic type of siloxane based SOG. One of the commonly used organic type SOG materials is a silicon oxide based polysiloxane which is featured with radical groups replacing or attaching to oxygen atoms. Based on these two basic structures, the molecular weight, the viscosity and the desirable film properties of SOG can be modified and adjusted to suit the requirement of specific IC fabrication process.
SOG film is typically applied to a pre-deposited oxide surface as a liquid to fill gaps and steps on the substrate. Similar to the application method for photoresist films, a SOG material can be dispensed onto a wafer and spun with a rotational speed which determines the thickness of the SOG layer desired. After the film is evenly applied to the surface of the substrate, it is cured at a temperature of approximately 400.degree. C. and then etched back to obtain a smooth surface in preparation for a capping oxide layer on which a second interlevel metal may be patterned. The purpose of the etch-back step is to leave SOG between metal lines but not on top of the metal, while the capping oxide layer is used to seal and protect SOG during further fabrication processes. The siloxane based SOG material is capable of filling 0.15 micron gaps and therefore it can be suitably used in 0.25 micron technology.
When fully cured, silicate SOG has similar properties like those of silicon dioxide. Silicate SOG does not absorb water in significant quantity and is thermally stable. However, one disadvantage of silicate SOG is the large volume shrinkage during curing. As a result, the silicate SOG retains high stress and cracks easily during curing and further handling. The cracking of the SOG layer can cause a serious contamination problem for the fabrication process. The problem can sometimes be avoided by the application of only a thin layer, i.e., 1000.about.2000 .ANG. of the silicate SOG material.
A typical process utilizing SOG material as an inter-metal dielectric (IMD) insulation is shown in FIGS. 1A.about.1E. As shown in FIG. 1A, a semiconductor structure 10 which has metal conductors 12, 14 built on a pre-processed semi-conducting substrate with an oxide layer 16 on top. The oxide layer may be suitably deposited of a boro-phospho-tetraethoxy-silicate (BPTEOS) material that is used to insulate previously deposited metal layers. The metal conductors 12, 14 are formed by first depositing a metal layer on a diffusion barrier layer (not shown) such as TiN before the deposition of an AlCu material. On top of the metal conductor material, an adhesion promoter layer such as Ti or TiN may also be deposited before an oxide cap layer 20 is used to insulate the metal conductors 12, 14. The oxide cap layer 20 may be deposited of a plasma enhanced oxide (PEOX) material. On top of the semiconductor structure 10, a first SOG layer 22 is then deposited to seal the metal conductors 12, 14 therein. Since SOG material has a large volume shrinkage ratio when it is deposited in a liquid form, the deposition step for SOG is preferably conducted in two separate stages for achieving a desirable thickness of SOG. The first SOG layer 22 is deposited and allowed to cure forming a dip 24 in its top surface 26. Prior to the second deposition step for SOG, an adhesion promoter layer (or a surfactant) is normally necessary to improve the adhesion of a liquid SOG to a cured SOG layer.
Since surfactant materials normally contain metal ions, especially calcium ions, calcium ions 30 are frequently left on the top surface 26 of the first SOG layer 22. This is shown in FIG. 2B. When a second SOG layer 32 is later deposited on top of the first SOG layer 22, the metal ions 30 are trapped at the interface 36 between the two SOG layers 22 and 32. Each of the SOG layers is deposited to a thickness of between about 2000 .ANG. and about 4000 .ANG., and preferably to 3000 .ANG. for achieving a total thickness of about 6000 .ANG.. This is shown in FIG. 1C.
In the next step of the process, the SOG layer 32 is etched back to approximately the interface 36 for achieving a planarized surface 38 such that the next insulating layer of PEOX 40, as shown in FIG. 1E, may be deposited. The undesirable metal ions 30 are thus trapped between the newly deposited PE oxide layer 40 and the first SOG layer 22. Protruded areas 42 in a top surface 44 of the PE oxide layer 40 are also formed due to the presence of the metal ions 30.
In a subsequent process wherein a via contact 50 is formed, a wet etch process is used to etch away the PE oxide layer 40 and the first SOG layer 22 after a via opening is first defined by a photolithographic process. During the wet etch process, the metal ions 30, i.e., calcium ions, can be easily etched away by the wet etchant and thus creating a void in the insulating layer. As a result, a large volume 48 of the first SOG layer 22 is etched away forming a large void. This type of void formation causes severe quality and reliability problems in the semiconductor devices built. A poor wafer yield is resulted from such defects.
Wafers prepared by the conventional technique shown in FIGS. 1A.about.1E were tested in a KLA.RTM. machine, data and wafer maps obtained are shown in Table 1 and FIGS. 2A.about.2F, respectively.
TABLE 1 #01 #02 #03 #04 #05 #06 #07 SOG Etch Back 2K 2.5K 4K 3.5K 4K 3K 2K Defect Count 146 1319 &gt;15000 &gt;15000 &gt;15000 &gt;5000 322
Wafer samples, after the double SOG deposition, are etched back to different thicknesses of the second SOG layer. For instance, sample 1 was etched back 2000 .ANG., sample 2 was etched back 2500 .ANG., sample 3 was etched back 4000 .ANG., sample 4 was etched back 3500 .ANG., sample 5 was etched back 4000 .ANG., sample 6 was etched back 3000 .ANG. and sample 7 was etched back 2000 .ANG.. Table 1 indicates that the defect count performed by the KLA.RTM. machine indicates that the maximum defect occurs at approximately the interface between the first SOG layer and the second SOG layer, i.e., at an etch depth of 3500 .ANG. or 4000 .ANG..
FIGS. 2A.about.2F show wafer maps obtained from KLA.RTM. machine wherein the maps were drawn by placing an ink dot at each defect location. When the SOG layer is etched back 2000 .ANG., as shown in FIG. 2A, very few defects are shown. When the etch-back increased to 2500 .ANG., the outside fringe of the wafer is normally etched faster than the center part of the wafer and therefore, the outside fringe has been etched away to almost 3000 .ANG., i.e., to a depth that is in close proximity to the SOG-1 and the SOG-2 interface. FIG. 2B therefore shows a wafer map wherein more defects are shown in an outer fringe of the wafer than the center part of the wafer. As the etch-back thickness increase to 3000 .ANG., as shown in FIG. 2C, the number of defects shown by the ink dots have greatly increased and once again, the outer fringe of the wafer showed more defects since the outer fringe was etched to a larger thickness. The most defects are observed in the wafer map obtained at an etch-back thickness of 3500 .ANG., as shown in FIG. 2D. This indicates that at the 3500 .ANG. etch-back thickness, the interface between the two SOG layers is reached. The defect count is slightly reduced at an etch-back depth of 4000 .ANG. from that observed at 3500 .ANG.. This is shown in FIG. 2E. The defect count greatly reduces when the etch-back thickness is increased to 4500 .ANG. therefore indicating that the etch-back process has progressed into the first SOG layer, and as such, defects caused by the metal ions at the interface no longer show.
It is therefore an object of the present invention to provide a method for insulating metal conductors by spin-on-glass that does not have the drawbacks or shortcomings of the conventional methods.
It is another object of the present invention to provide a method for insulating metal conductors by using spin-on-glass in inter-metal dielectric layers.
It is a further object of the present invention to provide a method for insulating metal conductors by spin-on-glass wherein a surfactant layer is utilized between two spin-on-glass layers by etching-back the second spin-on-glass layer and then scrub cleaning an exposed interface.
It is another further object of the present invention for insulating metal conductors by spin-on-glass wherein metal ion impurities existing at an interface between two spin-on-glass layers is effectively removed to eliminate void formation.
It is still another object of the present invention to provide a method for insulating metal conductors by spin-on-glass by incorporating a scrubber clean step after a spin-on-glass etch-back process for removing metal ion contaminants.
It is yet another object of the present invention to provide a method for forming inter-metal dielectric layers in a semiconductor structure by scrubber cleaning an interface between two spin-on-glass layers with a soft-bristle brush for removing metal ions.
It is still another further object of the present invention to provide a semiconductor structure that includes an inter-metal dielectric layer of spin-on-glass and an oxide insulating layer on top of the inter-metal dielectric layer without void formation thereinbetween.
It is yet another further object of the present invention to provide a method for forming inter-metal dielectric layers in a semiconductor structure by incorporating an additional processing step of scrubber clean an interface between two spin-on-glass layers with a polyvinyl alcohol (PVA) brush and water to substantially remove all residual metal ions at the interface.